1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to a method for implementing power gating in a logic block that includes N-nary dynamic logic (NDL) gates.
2. Description of the Related Art
Electronic devices and particularly those with modern processors are capable of consuming a great deal of power. To conserve battery life, in many systems it is becoming commonplace to turn off components that are not being used. Power gating, which is the term used to describe completely removing the voltage reference or the circuit ground reference from the component, is being widely used. This is in contrast to simply stopping the clock on a processor, for example. However, although power gating may be one of the most effective ways to reduce power consumption of a component, conventional power gating has some drawbacks particularly when dealing with dynamic or “domino” logic circuits that have more than one clock phase such as in 1-of-N or N-nary dynamic logic (NDL) circuits.
One such drawback is it is often difficult to determine how big to make the power gating transistors. More particularly, the power gating transistors need to be wide enough to carry the appropriate amount of current so that the voltage drop across the power gating transistors remains within design rules. In addition, the designer must ensure that the transistors are not so large that the power gating transistors take up unnecessary area. Further, optimal power gating row placement and distribution can be difficult.